Automatic formulation of design verification checks based upon a language representation of a hardware design to verify the intended behavior of the hardware design
US6539523B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a comprehensive set of design verification checks may be formulated by applying predetermined properties to an annotated hardware design representation. Information regarding the intended flow of logical signals in the hardware design is received by way of annotations in a control file or annotations embedded in the hardware design representation itself. The annotations include (1) an indication of one or more variables in the representation of the hardware design through which the logical signals pass, and (2) an indication of one or more conditions under which each of the one or more variables are to be associated with each of a set of states. Checks are then automatically formulated based upon a predetermined set of properties that must hold true in order for the hardware design to operate in accordance with the intended flow. Each of the checks is capable of evaluation with reference to the states associated with the one or more variables during propagation of the logical signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.