System and method of determining the noise sensitivity of an integrated circuit
US6539527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention includes an apparatus and a method of designing integrated circuits in which the susceptibility of the integrated circuit to noise is estimated by analyzing the components of the circuits. Suspected noise susceptibility factors were investigated to determine the effects of various potential factors on noise characteristics. It was determined that percent of “bad” capacitance to total capacitance of wire coupling pairs of components, the total length of the corresponding wires between pairs of components that are subject to capacitive coupling and driver output impedance of driving circuits each contributed significantly to noise factors in integrated circuits. It was also determined that the integrated circuit being analyzed can be analyzed as pairs of coupled components (drivers, receivers an interconnections between drivers and receivers) to which the noise susceptibility factors can be applied and used to determine the overall susceptibility of noise of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.