Method and apparatus for compiling source code by flattening hierarchies
US6539543B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1999 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Nov 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/456
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for optimizing the compilation of computer program by exposing parallelism are disclosed. The computer program contains steps which involve index expressions. The program also involves function calls. An index path in the program is identified by noting the steps involving index expressions. A non-hierarchical representation of the index path, including operations in the function calls is created and interrogated with questions relating to memory accesses. The results of the interrogation are stored in or back annotated to a question data structure. The method and apparatus preferably involve the use of a signal flow graph which is completed using the information in the question data structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.