Low RF loss direct die attach process and apparatus
US6541301B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Feb 12, 1999 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for electronically connecting a semiconductor device comprising a substrate having a backside surface and a top surface on which is formed active elements, to an electronic circuit board having at least two electrical contacts connected to sources of different potentials for communicating at least two different signals; the method comprising forming at least two through-wafer via holes on the backside surface of the semiconductor substrate beneath each of the active regions extending therethrough to the top surface; forming a conductive layer of material within each of the via holes extending therethrough, each of the conductive layers formed within the corresponding via holes being electrically separated from one another; the at least two electrical contacts on the circuit board congruently aligned with corresponding conductive layers and associated via holes; and attaching the circuit board to the semiconductor substrate at each of the corresponding electrical contacts and conductive layers so as to provide electrical communication of the first signal with one of the active elements on the substrate through at least one of the via holes and to provide electrical communic…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.