Method for fabricating polysilicon thin film transistor
US6541323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a polysilicon thin film transistor on a substrate includes forming a gate electrode on the substrate, forming a gate insulating layer on the gate electrode including the substrate, sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the gate insulating layer, forming a catalytic metal layer on the doped amorphous silicon layer by an ion doping method, simultaneously crystallizing the doped amorphous silicon layer and the intrinsic amorphous silicon layer so as to form a doped polysilicon layer and an intrinsic polysilicon layer, respectively, forming a source electrode and a drain electrode on the doped polysilicon layer, and removing a portion of the doped polysilicon layer between the source and drain electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.