Time multiplexing image processing functions for noise reduction
US6541751B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/778
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system on a chip for an image sensor includes a sensor array, a readout circuit, a data memory and a processor. The sensor array includes a two-dimensional array of pixel elements and a plurality of analog-to-digital conversion (ADC) circuits where each ADC circuit is coupled to one or more pixel elements in the sensor array. The readout circuit is coupled for reading the pixel data from the sensor array. The data memory is coupled for the sensor array for storing the pixel data. The processor is coupled for processing the pixel data. In operation, the system on a chip deactivates at least one noise-inducing circuit while a noise-sensitive circuit is activated. In one embodiment, the noise-sensitive circuit is one or more of the ADC circuits, and the noise-inducing circuit is one of the readout circuit, the data memory and the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.