Plasma display panel including grooves in phosphor
US6541914B1 · kind B1 · utility
2Cited by
6References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1999 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Nov 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J11/42
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A PDP minimizes a capacitance of phosphors by removing some of the phosphors of each discharge cell to maintain almost same discharge voltage level applied to discharge areas of each discharge cell. The PDP includes a plurality of lower electrodes successively formed on a first substrate in row direction, a plurality of isolation walls formed between the lower electrodes, a plurality of upper electrode sets successively formed on a second substrate opposite to the first substrate to cross the lower electrodes, and a phosphor formed on the first substrate to expose some of the lower electrodes crossed the upper electrode sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.