Low dropout voltage regulator with improved power supply rejection ratio
US6541946B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2002 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier 20 having a first input coupled to a reference voltage node Vref; a second amplifier 22 having an input coupled to an output of the first amplifier 20; a pass transistor 24 having a control node coupled to an output of the second amplifier 22; a feedback circuit 26 and 28 having an input coupled to the pass transistor 24 and an output coupled to a second input of the first amplifier 20; an inverting gain stage 36 coupled to the input of the second amplifier 22; and a high pass filter 42, 44, and 38 coupled between a power supply node and a control node of the inverting gain stage 36. The circuit uses the high pass filter 42, 44, and 38 and inverting gain stage 36 to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node Vo.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.