Reset first latching mechanism for pulsed circuit topologies
US6542006B1 · kind B1 · utility
6Cited by
31References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.