Duty cycle correction circuit and apparatus and method employing same
US6542015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage. The correction differential current is provided to the pair of summing nodes to produce a corrected differential current as the sum of the uncorrected differential current and the correction differential current so as to control the timing of the crossover of the corrected differential current at the pair of summing nodes to provide duty cycle correction. Finally, the corrected different…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.