Feed-forward approach for timing skew in interleaved and double-sampled circuits
US6542017B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal. Thus the clock generator circuit avoids sampling error in a double-sampled sample and hold circuit and harmonic distortion associated therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.