Highly linear and low noise figure mixer
US6542019B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Nov 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A new linearized transconductance circuit for converting an input into an output has been achieved. This linearized transconductance circuit is especially suited for application in a mixing circuit using a double-balanced cell. The circuit allows optimization of linearity and noise figure without excessive current. The input comprises first and second phases having a differential voltage therebetween. The output comprises first and second phases having a differential current therebetween that is proportional to the differential voltage. The circuit comprises, firstly, first, second, third, and fourth MOS transistors, with each transistor having a gate, a drain, and a source. The gates of the first and third MOS transistors are coupled to the input first phase. The drains of the first and third transistors are coupled to the output first phase. The gates of the second and fourth MOS transistors are coupled to the input second phase. The drains of the second and fourth MOS transistors are coupled to the output second phase. A first constant current source is coupled to the sources of the first and fourth MOS transistors. Finally, a second constant current source is coupled to the sou…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.