Digital to analog interface with equalized total signal delay and method of making it
US6542099B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Nov 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.