Field programmable processor arrays
US6542394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a field programmable circuit region arranged as a generally rectangular array of rows and columns of circuit areas. Some of the circuit areas each provide a respective processing unit for performing operations on data on at least one respective input signal path to provide data on at least one respective output signal path. Others of the circuit areas each provide a respective switching section; and the processing units and the switching sections are arranged alternately in each row and in each column. Each of a substantial proportion of the switching sections provides a programmable connection between at least some of the signal paths of those of the processing units adjacent that switching section in the same column and in the same row. A dense layout can be obtained with efficient local interconnections, especially in the case where one or more of the processing units has a plural-bit input and/or a plural-bit output, and at least some of the signal paths are provided by respective plural-bit busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.