Floating point pipeline with a leading zeros anticipator circuit
US6542915B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Presented is a “high-order” Leading Zeros Anticipator or LZA circuit and specifically a five-input LZA. The prior-art two-input LZA circuit is part of almost all high-performance floating-point units or FPUs. The advantages of a high-order LZA (such as five-input) is that the LZA function may be started and finished sooner in the floating point pipeline, and therefore allows more time for other functions in the pipeline. Therefore, a high-order LZA, such as five-input LZA, may be faster than the prior art two-input LZA designs. Thus, speeding up the LZA function in a floating point pipeline may significantly increase the speed in which the overall floating-point unit may operate as compared to the prior-art two input LZA designs and may additionally inspire new floating-point michroarchitectures which may yield further performance gains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.