Delay estimation for restructuring the technology independent circuit
US6543037B1 · kind B1 · utility
18Cited by
2References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.