Semiconductor integrated circuit with a reduced skew and layout method in design for semiconductor integrated circuit
US6543042B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Apr 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.