Electronic chip package
US6544638B2 · kind B2 · utility
112Cited by
73References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Sep 10, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/3154
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.