Method of fabricating semiconductor wafers having multiple height subsurface layers
US6544863B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Aug 21, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00619
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for fabricating semiconductor wafers as multiple-depth structure (i.e., having portions of varying height). The method includes patterning a first substrate and bonding a second substrate to the first. This process creates a subsurface patterned layer. Portions of the second substrate may then be etched, exposing the subsurface patterned layer for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. Or, for example, exposed portions of the first substrate may have material added to them to create multiple-depth structures. This method of fabrication provides substantial advantages over previous methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.