Nonvolatile semiconductor memory device
US6545909B2 · kind B2 · utility
73Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.