Memory configuration of a composite memory device
US6545916B2 · kind B2 · utility
7Cited by
16References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.