Negatively biased word line scheme for a semiconductor memory device
US6545923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Jul 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.