System and method for implementing error detection and recovery in a system area network
US6545981B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/326
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.