Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
US6546451B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1999 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Sep 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A node controller (12) includes a processor interface unit (24), a crossbar unit (26), and a memory directory interface unit (22). Request and reply messages pass from the processor interface unit (24) to the crossbar unit (26) through a processor interface output queue (52). The processor interface unit (24) writes a request message into the processor interface output queue (52) using a processor interface clock to latch a write address from a write address latch (62) in a synchronizer (60). The write address is encoded by a Gray code counter (64) and latched by a first sync latch (66) and a second sync latch (18) using a core clock of the crossbar unit (30). The output of the second sync latch (68) provides one of the inputs to a read address latch (70) using the core clock of the crossbar unit (30). The read address is provided to the processor interface output queue (52) so that the request message is presented to the crossbar unit (30) in its clock domain regardless of the clock frequency of the processor interface unit (24).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.