Method and apparatus for increasing data rates in a data network while maintaining system coherency
US6546464B2 · kind B2 · utility
37Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1999 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Jan 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0837
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising system memory and a cache memory maintain system coherency for data stored in a subset of memory elements utilizing software coherency control, while system coherency for all remaining memory elements is maintained utilizing hardware coherency control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.