Method of forming a storage node contact hole in a porous insulator layer
US6548348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02271
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for increasing the surface area of a DRAM capacitor structure via definition of a capacitor in a porous insulator layer, wherein the porous insulator layer is comprised with voids, has been developed. The process features the use of an anisotropic dry etch procedure to form a capacitor opening in a porous insulator layer, exposing a portion of the voids located on the sides of the capacitor opening extending into the porous insulator layer. An isotropic wet etch is then used to enlarge the surface area of the exposed voids, allowing the surface area for a subsequently formed, overlying storage node structure, to be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.