Method of vertically integrating electric components by means of back contacting

US6548391B1 · kind B1 · utility

Assignee

• Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V. · DE

Inventors

• Peter Ramm · St. Catharines, CA
• Armin Klumpp · Hersbruck, DE

Key dates

• Filing date: Mar 18, 2002
• Grant date: Apr 15, 2003
• Expiry date: Mar 18, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06541
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention relates to a method of connecting two semiconductor components comprising the steps of providing in a first main surface of a first semiconductor substrate first component structures including first contact areas, forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to the second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material on the first main surface of said first semiconductor substrate, forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes, providing on a second semiconductor substrate second component structures including second contact areas, forming second lands which are connected in an electrically conductive manner to the second contact areas, and connecting the first and the second semiconductor substr…