Method of fabricating interlevel connectors using only one photomask step
US6548400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jul 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted.As a technical advantage of the invention, each interconnection created by the method of the invention is a structure of wider trenches and narrower vias, wherein the diameter of the vias is approximately the same as the narrowest width of the reverse trench pattern, and each via is centered within the trench. The reverse trench pattern surrounding the via is approximately twice the width of the via diameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.