Patent · US Expired

Apparatus for wafer-level burn-in and testing of integrated circuits

US6548826B2 · kind B2 · utility

5Cited by
6References
6Claims
0Family size

Inventors

Key dates

Filing dateMar 22, 2001
Grant dateApr 15, 2003
Priority date—
Expiry dateMar 22, 2021

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/316
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.