Semiconductor memory device
US6548848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.