Lateral DMOS transistor integratable in semiconductor power devices
US6548863B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Oct 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.