Semicoductor passivation using barrier coatings
US6548912B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | May 15, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An encapsulated microelectronic device. The device includes a semiconductor substrate, microelectronic device adjacent to the semiconductor substrate, and at least one first barrier stack adjacent to the microelectronic device. The barrier stack encapsulates the microelectronic device. It includes at least one first barrier layer and at least one first polymer layer. The encapsulated microelectronic device optionally includes at least one second barrier stack located between the semiconductor substrate and the microelectronic device. The second barrier stack includes at least one second barrier layer and at least one second polymer layer. A method for making an encapsulated microelectronic device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.