Digital-to-analog converting device and method used in home networking system with compensation mechanism to reduce clock jitter
US6549157B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converting method operating under two clock signals of different periods is disclosed. The method includes steps of monitoring a phase relationship between the two clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and selecting one of the plurality of pre-stored sets of waveform samples to be converted into an analog signal according to the phase relationship. The various pre-stored series of waveform samples having therebetween phase differences are optionally used for phase compensation so as to reduce the clock jitter between the two clock signals. A digital-to-analog converter for implementing the above-mentioned method is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.