Data balancing scheme in solid state storage devices
US6549446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jan 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of ‘1’s and ‘0’s, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the ‘1’s and ‘0’s are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.