Memory cell having reduced leakage current
US6549451B2 · kind B2 · utility
6Cited by
2References
32Claims
0Family size
Inventor
Key dates
| Filing date | May 14, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | May 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the word lines comprise a negative voltage to reduce leakage current from the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.