RAM having dynamically switchable access modes
US6549483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.