MDSL DMT architecture
US6549512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A DMT device having an analog front end for receiving an analog signal, a converter for converting the analog signal to a digital signal, a FFT for converting the digital signal from the time domain to the frequency domain and feeding the digital signal to a frequency domain equalizer having variable coefficients for flattening the converted digital signal. The frequency domain equalizer includes a gain corrector coupled to the FFT to compensate the channel frequency rolloff and make each tone approximately the same amplitude before phase rotation and a phase rotator portion responsive to the output of the gain corrector to track small channel variation. Also included is circuitry for updating the coefficients of the frequency domain equalizer, preferably in the form of a slicer for controlling the frequency domain equalizer by feeding back an error signal thereto. The error signal is preferably fed back to the phase rotator portion of the frequency domain equalizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.