Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address
US6549960B1 · kind B1 · utility
17Cited by
19References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Nov 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.