Delayed transaction method and device used in a PCI system
US6549964B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.