Cascaded differential receiver circuit
US6549971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals. In one embodiment the differential receiver circuit further includes an inhibit circuit configured receive an inhibit control signal and to drive the p-channel devices gated to the first amplifier node and the n-channel devices gated to the second amplifier node to cutoff when the inhibit control signal is in a specified inhibit state. The inhibit circuit is preferably further configured to provide a low impedance path between the first amplifier node, the second amplifier node, and the feedback node…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.