Multi-bus access cache
US6549984B1 · kind B1 · utility
5Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are disclosed for providing concurrent access to first storage area and a second storage area. According to one embodiment, a device includes the first storage area. The device and the second storage area are both coupled to a first bus and are coupled together by a dedicated second bus. According to one embodiment, a snoop operation on the first storage area be preferred concurrently with a snoop operation on the second storage area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.