Pipelined SDRAM memory controller to optimize bus utilization
US6549991B1 · kind B1 · utility
16Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
All memory commands are classified into two categories: background commands and foreground commands, depending on whether they are data related or not. The pointed background command and foreground commands are issued onto the DRAM bus at the earliest time when the required constrains are met. The background and foreground FSM controllers work in a pipelined or overlapped manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.