Memory clock generator and method therefor
US6550013B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1999 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Sep 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.