Hybrid multiple redundant computer system
US6550018B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid multiple redundant computer system (10) having at least three parallel operating processing units (12) including input module (14), central processor module (16), and output module (50) in each processing unit is disclosed. The central processor module (16) is connected to the associated input module (14) and connected to primary and secondary output circuits (18, 20) located in the associated output module (50) and in the neighboring output module (50) respectively. Each processing unit (12) further includes a watchdog controller (30) that monitors the associated central processor module (16) and transfers an alarm signal (44) to each output module (50) in the event that a central processor module (16) fails. Primary and secondary output circuits (18, 20) in each output module (50) control an output voter network (22) and perform selectable but different logical functions among output data of the respective central processor modules (16) and alarm signals (44) for providing no single point of failure within the output module (50). If alarm signals (44) are not activated, the system generates an output (180) using two-of-three vote among output data produced by three centr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.