Testing system and methods with protocol pattern injection and external verification
US6550029B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1999 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Oct 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2801
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method of testing processor boards in which a test path is created by setting switches in distribution hubs and the devices under test. Test signals are sent through the test path and errors in the signals are used to identify faulty boards. The distribution hubs of an embodiment can detect, report and eliminate errors in the test signals. A command path from a host to the distribution hubs and devices under test is provided through a multi-terminal connector. The command path is preferably separate from the test path. A test signal generator may be included. The system may be particularly adapted for fiber channel testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.