Method for designing a decoupling circuit
US6550037B2 · kind B2 · utility
5Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | May 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupling capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage, and determining the inductance of the source line based on the impedance of the decoupling capacitor and the allowable minimum multiplexing ratio of the source current by the decoupling capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.