Hardware/software co-synthesis of heterogeneous low-power and fault-tolerant systems-on-a chip
US6550042B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Mar 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present co-synthesis technique takes as an input embedded system specification in terms of acyclic task graphs, system constraints, and a resource library consisting of several functional blocks such as processor cores, memory, proprietary and non-proprietary functional blocks, and generates a low-cost hardware and software architecture for systems-on-a-chip such that all real time constraints are met while minimizing average power dissipation. It employs a floor-planning based delay estimator during evaluation of various architectures. Actual delay measurements made on synthesized chips indicate that the delay estimator error is less than 12%. The technique can be extended to derive fault-tolerant architectures for systems-on-a-chip employed in critical applications. Fault-detection capability is imparted to the system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. Error recovery is achieved by switching to spare functional blocks. The reliability and availability of the architecture are evaluated during co-synthesis using Markov models. Application of the technique to examples from real-life systems such a cellular h…
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