Power MOS transistor having increased drain current path
US6552393B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/615
Abstract
A power MOS transistor that permits a large current to flow without a broad gate width being employed. The power MOS transistor includes a substrate of a first conductivity type; a well region of a second conductivity type; a first electrode region whose impurity concentration is higher than the well region; a region of a first conductivity type; and a second electrode region. The first electrode region, first-conductivity-type region and second electrode region are respectively arranged in this order spaced apart from one another in a first direction. The first-conductivity-type region includes a plurality of first-conductivity-type sub-regions, which are provided spaced apart from one another in a second direction that is orthogonal to the first direction. A surface channel region is formed between adjacent first-conductivity-type sub-regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.