Techniques for addressing cross-point diode memory arrays
US6552409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.