Power switching semiconductor device with suppressed oscillation
US6552429B2 · kind B2 · utility
7Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Oct 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wiring pattern (26) or (27) and conductor wires (W1, W2) or (W3, W4) not relaying a wiring pattern (22) or (23) fed with an emitter current connect emitter electrodes of a plurality of IGBTs (3) connected in parallel with each other. Thus, oscillation appearing on the potential of a control electrode of the plurality of IGBTs (3) is suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.